20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

Proc. SPIE 4116, 300 (2000); http://dx.doi.org/10.1117/12.406508

Conference Date: Wednesday 02 August 2000
Conference Location: San Diego, CA, USA
Conference Title: Advanced Signal Processing Algorithms, Architectures, and Implementations X
Conference Chairs: Franklin T. Luk
Richard L. Walke and Robert W. M. Smith

Defence Evaluation and Research Agency Malvern (United Kingdom)

Gaye Lightbody

Queen's Univ. of Belfast (United Kingdom)

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

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Citation
Richard L. Walke, Robert W. M. Smith and Gaye Lightbody, "20-GFLOPS QR processor on a Xilinx Virtex-E FPGA", Proc. SPIE 4116, 300 (2000); http://dx.doi.org/10.1117/12.406508
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