Lightbody, G, Walke, R, Woods, R and McCanny, J (2000) Linear QR Architecture for a Single Chip Adaptive Beamformer. The Journal of VLSI Signal Processing, 24 (1). pp. 67-81. [Journal article]
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This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
|Item Type:||Journal article|
|Keywords:||VLSI, systolic arrays, QR, RLS, mapping|
|Faculties and Schools:||Faculty of Computing & Engineering|
Faculty of Computing & Engineering > School of Computing and Mathematics
|Deposited By:||Dr Gaye Lightbody|
|Deposited On:||17 Apr 2012 08:48|
|Last Modified:||09 Dec 2015 10:45|
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