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Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

Lightbody, G, Woods, R and Francey, J (2007) Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators. In: 2007 International Conference on Field Programmable Logic and Applications, Amsterdam. IEEE. 4 pp. [Conference contribution]

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URL: http://dx.doi.org/10.1109/FPL.2007.4380725

DOI: doi:10.1109/FPL.2007.4380725

Abstract

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

Item Type:Conference contribution (Poster)
Keywords:QR, RLS, VLSI, multiplicative division, mapping architectures
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Mathematics
ID Code:12273
Deposited By: Dr Gaye Lightbody
Deposited On:17 Apr 2012 08:40
Last Modified:09 Dec 2015 10:45

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