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Low-power synthesis flow for regular processor design

Woods, R, Lightbody, G, Cassidy, A, Keane, G and Spanier, J (2001) Low-power synthesis flow for regular processor design. In: IEE Seminar Low Power IC Design, London, UK, 19 Jan. 2001. IET. 5 pp. [Conference contribution]

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URL: http://digital-library.theiet.org/getabs/servlet/GetabsServlet?prog=normal&id=IEESEM002001000042000012000001&idtype=cvips&gifs=yes&ref=no

DOI: http://dx.doi.org/10.1049/ic:20010018


The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits for data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative "low-power" project involving the universities of Liverpool Manchester and Sheffield. The design flow is briefly described and some results are presented for multiplier implementations and their use in the development of a discrete cosine transform (DCT) circuit

Item Type:Conference contribution (Paper)
Keywords:Low power, VLSI, systolic arrays
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Mathematics
ID Code:12274
Deposited By: Dr Gaye Lightbody
Deposited On:17 Apr 2012 08:46
Last Modified:09 Dec 2015 10:45

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