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Generic SoC QR array processor for adaptive beamforming

Zhaohui, L, McCanny, J V, Lightbody, G and Walke, R (2003) Generic SoC QR array processor for adaptive beamforming. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50 (4). pp. 169-175. [Journal article]

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URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1193571

DOI: doi:10.1109/TCSII.2003.810487


A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.

Item Type:Journal article
Keywords:QR, RLS, VLSI, scheduling, mapping, systolic arrays
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Mathematics
ID Code:12280
Deposited By: Dr Gaye Lightbody
Deposited On:17 Apr 2012 08:38
Last Modified:09 Dec 2015 10:45

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