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FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic

Meher, PK, Chandrasekaran, S and Amira, A (2008) FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE TRANSACTIONS ON SIGNAL PROCESSING, 56 (7, Par). pp. 3009-3017. [Journal article]

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DOI: 10.1109/TSP.2007.914926


In this paper, we present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay-power-efficient implementation of finite-impulse-response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA-based computation to decide on suitable area time tradeoff. It is observed that by using smaller address lengths for DA-based computing units, it is possible to reduce the memory size, but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density, and energy throughput are estimated for different filter orders and address lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address length M = 4 yields the best of area-delay-power-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.

Item Type:Journal article
Keywords:distributed arithmetic; field-programmable gate arrays (FPGA); finite-impulse-response (FIR) filter; linear convolution; systolic array
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Engineering
Research Institutes and Groups:Engineering Research Institute
Engineering Research Institute > Nanotechnology & Integrated BioEngineering Centre (NIBEC)
ID Code:13405
Deposited By: Dr Abbes Amira
Deposited On:20 May 2010 10:36
Last Modified:25 Jul 2011 11:28

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