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Novel FPGA implementations of Walsh-Hadamard transforms for signal processing

Amira, A, Bouridane, A, Milligan, P and Roula, M (2001) Novel FPGA implementations of Walsh-Hadamard transforms for signal processing. IEE PROCEEDINGS-VISION IMAGE AND SIGNAL PROCESSING, 148 (6). pp. 377-383. [Journal article]

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DOI: 10.1049/ip-vis:20010674


The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.

Item Type:Journal article
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Engineering
Research Institutes and Groups:Engineering Research Institute
Engineering Research Institute > Nanotechnology & Integrated BioEngineering Centre (NIBEC)
ID Code:13472
Deposited By: Dr Abbes Amira
Deposited On:20 May 2010 10:34
Last Modified:25 Jul 2011 11:28

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