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Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures

Amira, A, Bouridane, A, Milligan, P and Belatreche, A (2002) Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 149 (1). pp. 17-24. [Journal article]

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DOI: 10.1049/ip-cdt:20020159

Abstract

Discrete orthogonal transforms (DOTs) are important in many applications, including image and signal processing. Novel 1D and 2D bit-level systolic architectures are presented for the efficient implementation of DOTs for image and signal processing. The authors describe the design methodology of the techniques based on the Baugh-Wooley algorithm, and the associated design including a case study of an FPGA implementation. They also discuss the efficiency of implementations which have O(N-2) and O(2nN) as the area and time complexities for 2D structures, respectively, and O(N) and O(2nN) as the area and time complexities for 1D structures, respectively (where N is the transform length and n is the word length). Furthermore, it is shown that the architectures are parameterisable and that the area required by the designs can be predicted for different values of N and n. A comparison with existing and similar structures has shown that the proposed architectures perform better.

Item Type:Journal article
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Engineering
Research Institutes and Groups:Engineering Research Institute
Engineering Research Institute > Nanotechnology & Integrated BioEngineering Centre (NIBEC)
ID Code:13473
Deposited By: Dr Abbes Amira
Deposited On:20 May 2010 10:40
Last Modified:25 Jul 2011 11:28

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