Pande, Sandeep, Morgan, Fearghal, McCawley, Seamus, McGinely, Brian, Carrillo, Sanider, Harkin, Jim and McDaid, Liam (2010) EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures. In: International Symposium on System-on-Chip (SoC), Finland. IEEE. 7 pp. [Conference contribution]
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This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.
|Item Type:||Conference contribution (Paper)|
|Faculties and Schools:||Faculty of Computing & Engineering|
Faculty of Computing & Engineering > School of Computing and Intelligent Systems
|Research Institutes and Groups:||Computer Science Research Institute|
Computer Science Research Institute > Intelligent Systems Research Centre
|Deposited By:||Dr Jim Harkin|
|Deposited On:||29 Oct 2010 10:10|
|Last Modified:||09 May 2016 11:02|
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