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Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations

Carrillo, S, Harkin, JG, McDaid, LJ, Pande, S, Cawley, S, McGinley, B and Morgan, F (2012) Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. In: ACM/IEEE International Symposium on Networks-on-Chip (NoC), Denmark. IEEE. 8 pp. [Conference contribution]

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The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

Item Type:Conference contribution (Paper)
Keywords:Network-on-Chip, Traffic Compression, Spiking Neural Network, hardware
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Intelligent Systems
Research Institutes and Groups:Computer Science Research Institute > Intelligent Systems Research Centre
Computer Science Research Institute
ID Code:21155
Deposited By: Dr Jim Harkin
Deposited On:10 May 2012 12:36
Last Modified:10 May 2012 12:36

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