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Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware

Liu, J, Harkin, J, McDaid, LJ and Martin, G (2016) Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware. In: 25th International Conference on Artificial Neural Networks. Springer. 8 pp. [Conference contribution]

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URL: http://icann2016.org/

DOI: 10.1007/978-3-319-44778-0

Abstract

Scalable hardware interconnect is a significant research challenge for neuromorphic systems in particular, this becomes more pronounced when we seek to realise the integration of neurons with astrocytes cells. This paper pre-sents a novel interactive architecture for the astrocyte-neuron network (ANN) hardware systems, and the novel Hierarchical Astrocyte Network Architecture (HANA) using networks-on-chip (NoC) for the efficient information exchange between astrocyte cells. The proposed HANA incorporates a two-level NoC packet transmission mechanism to increase the information exchange rate be-tween astrocyte cells and to provide a NoC traffic balance for local and global astrocyte networks. Experimental results demonstrate that the proposed HANA approach can provide efficient information exchange rates for the ANN, while the hardware synthesis results using 90nm CMOS technology show that it has a low area overhead which maintains scalability.

Item Type:Conference contribution (Paper)
Keywords:Astrocyte-neuron network; networks-on-chip, interconnect; self-repair; FPGAs
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Intelligent Systems
Faculty of Computing & Engineering > School of Computing and Mathematics
Research Institutes and Groups:Computer Science Research Institute > Intelligent Systems Research Centre
Computer Science Research Institute
Computer Science Research Institute > Artificial Intelligence and Applications
ID Code:34924
Deposited By: Dr Jim Harkin
Deposited On:01 Aug 2016 13:58
Last Modified:17 Oct 2017 16:24

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