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Investigation of Programmable Threshold Logic Gate Array

Kelly, Peter, Thompson, C.J., McGinnity, TM and Maguire, Liam (2002) Investigation of Programmable Threshold Logic Gate Array. In: IEEE 9th International Conference on Electronics, Circuits and Systems, 2002.. UNSPECIFIED. 4 pp. [Conference contribution]

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DOI: 10.1109/ICECS.2002.1046258


A study of simulated InP-based RTD/HFET threshold logic gates (TLGs), deployed in an array suited to the implementation of programmable neural network-like architectures, is carried out. A new programmable TLG and an EX-OR TLG are presented. An array of programmable and non-programmable TLGs is studied to demonstrate an application with field programmability and to determine the suitability of the technology for the realisation of these gates in larger scale integrated circuits. The architecture may have the potential for a flexible platform that will allow training and reconfiguration of a cellular artificial neural network (ANN). The functionality of the circuit architecture is investigated and the effects of variations in device-characteristics, and clocked power supply on its operation are considered to assess the potential use of TLG circuits in the context of larger scale implementations.

Item Type:Conference contribution (Paper)
Faculties and Schools:Faculty of Computing & Engineering
Faculty of Computing & Engineering > School of Computing and Intelligent Systems
Research Institutes and Groups:Computer Science Research Institute
Computer Science Research Institute > Intelligent Systems Research Centre
ID Code:7916
Deposited By: Professor Martin McGinnity
Deposited On:04 Feb 2010 14:43
Last Modified:23 Jun 2011 10:27

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